Agilent Technologies has announced a strategic partnership with Aster Technologies to enable integration of Aster's TestWay Coverage Analyst with Agilent's printed-circuit-board assembly-test ...

The complexity of system-on-chip (SoC) designs continues to grow, so the corresponding design-for-test (DFT) logic required for manufacturing has become more advanced. Design teams are challenged by ...

While the analog and mixed-signal components are the leading source of test escapes that result in field failures, the lack of tools to analyze the test coverage during design has made it difficult ...

February 5, 2013. ASTER Technologies, a supplier of board-level testability and test-coverage analysis products, has developed a new release of TestWay in support of “Design for Excellence” (DfX) ...

Asset InterTech has announced its DFT Analyzer, which according to the company reduces manufacturing and test costs by validating the boundary-scan design-for-test features in a circuit-board design ...

Scan is a structured test approach in which the overall function of an integrated circuit (IC) is broken into smaller structures and tested individually. Every state element (D flip-flop or latch) is ...